A CDR circuit is commonly used in a high speed data communication system. Generally, the high speed data communication system receives data without an accompanying clock signal. An absence of the accompanying clock signal may result in undersampling or oversampling of the data. Thus, a CDR circuit is used in the high speed data communication system to generate a clock signal that is phase and frequency synchronized with the data. Further, the high speed data communication system samples the data at the frequency of the clock signal.
A Passive optical network (PON) is an example of the high speed data communication system that employs CDR circuits for generating the clock signal that is frequency and phase synchronized with the data. The PON typically includes an optical line terminal (OLT) for communicating with multiple optical network units (ONUs). In downstream data transmission, the OLT is connected to a splitter by way of a fiber optic cable. The splitter receives downstream data from the OLT, splits the downstream data into a plurality of data streams, and transmits the plurality of data streams simultaneously to the multiple ONUs. In upstream data transmission, each ONU transmits corresponding upstream data in burst mode to a combiner one at a time. The combiner receives the corresponding upstream data from each of the ONUs by way of the fiber optic cable and transmits the corresponding upstream data to the OLT.
The OLT transmits downstream data to the multiple ONUs in continuous mode. Hence, CDR circuits in the multiple ONUs have sufficient time to get frequency and phase synchronized to the downstream data. However, upstream data transmitted by the multiple ONUs to the OLT are transmitted in burst mode. Burst mode is a temporary high-speed data transmission mode used for facilitating sequential data transfer at a high throughput. Burst mode data transfer speed is typically two to five times faster than continuous mode data transfer speed. Since a large amount of upstream data is sent by the multiple ONUs in a short period of time, a CDR circuit on the OLT must be frequency and phase synchronized to the upstream data. If the phase of the clock signal is not synchronized to the upstream data, the clock signal may oversample the upstream data, and the periodicity of the clock signal may vary over multiple clock cycles. Variations in the periodicity of the clock cycle may lead to jitter in the upstream data. Jitter in the upstream data is undesirable as it may lead to data loss. Further, the clock signal may be staggered with respect to the data. Hence, the clock signal must be frequency and phase synchronized to the upstream data in a short time to avoid staggering of the clock signal and jitter in the upstream data.
CDR circuits are further employed in a low latency interface (LLI) system for performing clock and data recovery. The LLI system provides a point-to-point interconnect between two components on devices such as a mobile phone, a central processing unit, and the like. In one example, the two components are a processor and a memory. The processor may be a processor such as a baseband processor, a graphics controller, a digital signal processor, and the like. The memory may be a memory such as a random access memory, a flash memory, and the like. The processor transmits and receives the data in burst mode by way of a direct mode access (DMA) controller. Typically, a common clock is provided in the device for the processor and the DMA controller. Since a common clock is provided for the processor and the DMA controller, the processor and the DMA controller are frequency synchronized. However, the data received or transmitted by the processor from the memory or to the memory may have a phase difference with a phase of the common clock. Hence, the CDR circuit with fast phase synchronization is imperative to avoid data loss caused due to staggering and jitter.
Conventional bang-bang (BB) (Alexander) CDR circuits are employed for frequency and phase locking in various digital systems. A known implementation of the BBCDR circuit includes a bang-bang phase detector (BBPD), proportional and integral control circuits, and a voltage controlled oscillator (VCO). The BBPD determines whether a clock signal generated by the VCO is early or late with respect to an input signal. If a rising edge of the clock signal arrives before a transition of the input signal from a first logic state to a second logic state, the clock signal is early with respect to the input signal. If the rising edge of the clock signal arrives after the transition of the input signal from the first logic state to the second logic state, the clock signal is late with respect to the input signal. The BBPD further generates an early-late signal based on whether the clock signal is early or late with respect to the input signal.
The BBPD is further connected to the proportional and integral control circuits. The proportional and integral control circuits receive the early-late signal and generate proportional and integral control signals, respectively, for controlling the VCO. The VCO further generates the clock signal based on the proportional and integral control signals. The proportional control signal controls the phase of the clock signal. The integral control signal controls the frequency of the clock signal. However, the integral control circuit introduces delays in generation of the integral control signal. The delay in a settling time of the integral control signal delays the phase locking of the clock signal to the data. This causes the clock signal to be staggered, and further introduces jitter in the data. Another implementation of the CDR circuit employs a phase-interpolator for generating the clock signal that is frequency and phase synchronized to the data. The phase interpolator is further controlled by way of the proportional and integral control signals. The integral control signal hinders fast locking of the clock signal to the data in both VCO-based and PI-based implementations.
To overcome the aforementioned problems, a gated VCO CDR circuit, an oversampling CDR circuit, and a blind CDR circuit may be used for achieving phase synchronization with the data in a short time. The gated VCO CDR circuit employs two VCOs for generating a clock signal that is frequency and phase synchronized to the data. However, employing two VCOs in the gated VCO CDR circuit increases its design complexity and further leads to high power consumption by the gated VCO CDR circuit. The oversampling CDR circuit employs a sampling clock signal at a high frequency for sampling the data and generating sampled data. Based on the sampled data, the oversampling CDR circuit generates the clock signal. In one example, the sampling clock signal is used to sample the data six times in one clock cycle. If the clock signal has a frequency of 10 MHz, then the sampling clock signal needs to have a frequency of 60 MHz. Hence, the oversampling CDR circuit introduces jitter in the data when employed for very high speed clock signals. The blind CDR circuit samples the data with an asynchronous clock signal to generate sampled data. The blind CDR circuit further uses a digital interpolator for recovering the data from the sampled data. The blind CDR circuit requires complex mixed signal and digital circuits such as an analog-to-digital converter, the digital interpolator and the like. The blind CDR circuit further consumes high power.
Hence, it would be advantageous to have a CDR circuit that performs fast phase locking, prevents jitter in the recovered data and prevents staggering of the recovered clock, and consumes less power.